Enhancing Flip-Chip Technology: Addressing Thermal Expansion Challenges with Innovative Underfill Solutions

The introduction of novel substrate materials has presented flip-chip technology with fresh obstacles. Engineers are tasked with resolving issues stemming from the disparity in thermal expansion coefficients between the die and substrate to prevent the edges of joints from cracking during reflow soldering operations.

Wafer & Flip-chip Underfilling Challenges

Flip-chip technology stands out among various sophisticated die-attach methods as the preferred choice for compact 6C electronic devices. This preference comes as larger, high-efficiency chips emerge and flip-chip assemblies begin utilizing novel, non-ceramic materials, challenging the conventional techniques that have been in place for two decades. The primary issue arises from the mismatch in thermal expansion coefficients (CTE) between the chip and its non-inorganic substrate.

Specifically, flip chips crafted from silicone exhibit a significantly lower CTE compared to standard substrate materials like PCBs, leading to relative movements during thermal cycling tests. This discrepancy often results in mechanical stress that can detach or fracture solder joints.

In recent times, this approach has been adopted for certain BGA and CSP chips to enhance their drop resistance reliability. Epoxy resin is typically employed as an underfill to bolster the solder joints’ mechanical robustness and extend the chip’s lifespan. This resin is applied around the chip’s perimeter, seeping beneath the flip chip or BGA before being heat-cured to fortify solder joint durability significantly. Such an application is increasingly common in handheld device circuitry, including smartphones, which must endure multiple drop-and-tumble tests. Given these stringent testing conditions, numerous BGA solder connections struggle to meet requirements, particularly those on ENIG boards.

The underfill process is strategically placed after assembling the circuit board to avoid complications with subsequent repairs or reworking of wafers. Therefore, it’s crucial that all SMT processes, wave soldering, and manual soldering operations are thoroughly vetted through electrical testing post-completion to ensure the board functions flawlessly before proceeding with underfilling. This step ensures that any potential issues are addressed beforehand since accessing components becomes challenging once underfill has been applied.


Applying underfill material to a substrate requires maintaining the surface temperature of both the substrate and die between 70°C and 90°C. This specific temperature range promotes airflow upwards from beneath the wafer, altering its surface energy, which helps minimize the underside warping of the wafer.

The creation of filling bubbles during this process is crucial for preventing paint degradation over time, ensuring that the underfill material adequately fills beneath the die. Deviating from this temperature range can cause air to descend, forming undesirable bubbles. In subsequent high-temperature reflow processes, solder balls may lead to tin whiskering and potentially result in electrical leakage issues.


GLUDITEC epoxy resin, designed for flip-chip encapsulation, addresses these concerns while supporting lead-free requirements. It offers versatility in curing methods—suitable for both high and low temperatures—and aligns with various environmental standards including RoHS, Halogen Free, REACH, and GP.

Characteristics such as minimal curing shrinkage, low ion release rate, high glass transition temperature, reduced thermal expansion coefficient, robust elastic modulus, and diminished post-curing stress ensure that wafers achieve strong bonding and reliability post-curing.

Furthermore, this resin series is engineered to support advanced microchip bonding and copper pillar bump packaging technologies by accommodating extremely fine gaps due to its variable powder content. It exhibits rapid flow through narrow ball gaps while maintaining excellent electrical properties like low dielectric constant and high dielectric strength alongside superior chemical resistance. Fully compatible with wafer-level packaging (WLP) as well as Ball Grid Array (BGA) and Chip Scale Packaging (CSP) components, these resins are optimal for flip-chip applications.

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